关键字:TMS320LF2407解密/ TMS320LF2407破解
TMS320LF2407解密/ TMS320LF2407破解

时间:2011-06-17

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  介绍了在DSP基础上,实现数字图像的混沌加密及硬件实现方法。根据离散化和数字化处理技术,对三维Lorenz混沌系统作离散化处理,用C语言和DSP技术产生三维Lorenz混沌迭代序列,分别对数字图像的红、绿、蓝三基色信号进行混沌加密和解密。基于芯片型号为TMS320VC5509A的DSP开发平台,以bmp格式的灰度图像为例,设计了Lorenz混沌序列对数字图像进行加密与解密算法,给出了DSP硬件实现结果表明,改善了安全性、提高了速度、满足了实时性要求。

在成功突破TI系列多个型号DSP芯片解密的基础上,领卓科技现面向国内外各类客户提供TMS320LF2407解密等TI公司的TMS320F2401系列、TS320LF2406系列DSP芯片解密

这里,我们提供对TMS320LF2407 DSP芯片的功能特征详解,帮助客户及解密工程师充分理解芯片内部结构与加解密特征,有TMS320LF2407解密等DSP芯片解密需求者欢迎与领卓科技联系咨询更多合作详情


    TMS320LF2407 FEATURES

 High-Performance Static CMOS Technology

  – 33-ns Instruction Cycle Time (30 MHz)

  – 30 MIPS Performance

  – Low-Power 3.3-V Design

  Based on T320C2xx DSP CPU Core

  – Code-Compatible With ’F243/’F241/’C242

  – Instruction Set and Module Compatible With ’F240/’C240

  – Source-Code-Compatible With TMS320C1x/2x

  Flash (LF) and ROM (LC) Device Options

  – ’LF240x?: ’LF2407, ’LF2406, ’LF2402

  – ’LC240x?: ’LC2406, ’LC2404, ’LC2402

  On-Chip Memory

  – Up to 32K Words x 16 Bits of Flash EEPROM (4 Sectors) or ROM

  – Up to 2.5K Words x 16 Bits of Data/Program RAM

  – 544 Words of Dual-Access (DARAM)

  – 2K Words of Single-Access (SARAM)

  Boot ROM (’LF240x Devices)

  – SCI/SPI Flash Bootloader

  Two Event-Manager (EV) Modules (A and B) EVA and EVB Each Include:

  – Two 16-Bit General-Purpose Timers

  – Eight 16-Bit Pulse-Width Modulation(PWM) Channels Which Enable:

  – Three-Phase Inverter Control

  – Centered or Edge Alignment of PWM Channels

  – Emergency PWM Channel Shutdown With External PDPINT Pin

  – Programmable Deadband Prevents Shoot-Through Faults

  – Three Capture Units For Time-Stamping of External Events

  – On-Chip Position Encoder Interface Circuitry

  – Synchronized Analog-to-Digital Conversion

  – Suitable for AC Induction, BLDC,Switched Reluctance, and Stepper Motor Control

  – Applicable for Multiple Motor and/or Converter Control

  External Memory Interface (’LF2407)

  – 192K Words x 16 Bits of Total Memory,64K Program, 64K Data, 64K I/O

  Watchdog (WD) Timer Module

  10-Bit Analog-to-Digital Converter (ADC)

  – 8 or 16 Multiplexed Input Channels

  – 500 ns Minimum Conversion Time

  – Selectable Twin 8-Input Sequencers Triggered by Two Event Managers

  Controller Area Network (CAN) 2.0B Module

  Serial Communications Interface (SCI)

  16-Bit Serial Peripheral Interface (SPI)Module (Except ’x2402)

  Phase-Locked-Loop (PLL)-Based Clock Generation

  Up to 40 Individually Programmable,Multiplexed General-Purpose Input/Output (GPIO) Pins

  Five External Interrupts (Power Drive Protection, Reset, and Two Maskable Interrupts)

  Power Management:

  – Three Power-Down Modes

  – Ability to Power-Down Each Peripheral Independently

  Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1? (JTAG)

  Development Tools Include:

  – Texas Instruments (TIE) ANSI C Compiler, Assembler/Linker, and Code ComposerE Debugger

  – Evaluation Modules

  – Scan-Based Self-Emulation (XDS510E)

  – Numerous Third-Party Digital Motor Control Support

  Package Options

  – 144-Pin Thin Quad Flatpack (TQFP) PGE (’LF2407)

  – 100-Pin TQFP PZ (’LC2404, ’LC2406,’LF2406)

  – 64-Pin PQFP PG (’LC2402 and ’LF2402)

  Extended Temperature Options (A and S)

  – A: – 40°C to 85°C

  – S: – 40°C to 125°C


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